The present invention relates to a method of forming a semiconductor memory device, and more particularly to a method of forming a non-volatile semiconductor memory device having a high density integration of size-reduced memory cells having floating gate MOS field effect transistors with an accurately controlled gate length.
FIG. 1 is a fragmentary circuit diagram illustrative of a partial array structure of memory cells having floating gate MOS field effect transistors in the conventional non-volatile semiconductor memory device. Each of the memory cells CELL comprises a pair of a storage capacitor and a floating gate MOS field effect transistor. The memory cell array has a plurality of bit lines BL extending in a first direction. The memory cell array also has a plurality of word lines WL extending in a second direction perpendicular to the first direction. The memory cell array comprises a plurality of memory cell columns, each of which extends along the first direction and between adjacent two of the bit lines BL. Since each of the memory cells has the single pair of the floating gate MOS field effect transistor and the storage capacitor, each of the memory cell columns has a plurality of the floating gate MOS field effect transistors. Each of the floating gate MOS field effect transistors has a source, a drain, a floating gate and a control gate. Sources of the floating gate MOS field effect transistors in the each memory cell column are commonly connected to each other through a common source line. Drains of the floating gate MOS field effect transistors in the each memory cell column are also commonly connected to each other through a common drain line. This common drain line is further connected through a drain selecting transistor SWD to the corresponding bit line BL. The drain selecting transistor SWD has a gate connected to a drain selector line DSEL, so that the common drain line is made connected to the bit line BL in accordance with a drain selecting signal transmitted on the drain selector line DSEL connected to the gate of the drain selecting transistor SWD. A source line SL is further provided which extends in the second direction. The above common source line is connected through a source selecting transistor SWS to the source line SL. The source selecting transistor SWS has a gate connected to a source selector line SSEL, so that the common source line is made connected to the source line SL in accordance with a source selecting signal transmitted on the source selector line SSEL connected to the gate of the source selecting transistor SWS. Each of the memory cell rows comprises the plural floating gate MOS field effect transistors having control gate electrodes connected to the corresponding word line WL. The above circuit configuration forms an AND-type memory. In accordance with the AND-type memory, it is necessary that the sources and drains of the floating gate MOS field effect transistors on the memory cell column TCELLm are separated from the sources and drains of the floating gate MOS field effect transistors on the adjacent memory cell column TCELLn. It is necessary that the control gate electrodes serving as the word line extend in the gate length direction. By contrast to the AND-type memory, a NOR-type memory has a different structure that the source regions of the floating gate MOS field effect transistors on the each memory cell column are common to each other, whilst the drain regions thereof serve as the bit line. A contact is provided for every one or plural memory cells. For these reasons, the control gates of the floating gate MOS field effect transistors extend in the gate width direction. Since as described above, the AND-type memory has the structure that the control gate electrodes serving as the word line extend in the gate length direction, it is impossible that after the control gate and the floating gate have been formed, then the source and drain region are formed. It is necessary for the AND-type memory that the floating gate is firstly formed and then the source and drain regions are secondly formed before the control gate is finally formed.
FIGS. 2A through 2E are fragmentary cross sectional elevation views illustrative of the first conventional method of forming the floating gate MOS field effect transistor included in the AND-type memory. This first conventional method is the applicant""s admitted prior art.
With reference to FIG. 2A, shallow trench isolations 202 are selectively formed in an upper region of a p-type silicon substrate 201 thereby to define a memory cell formation region 220 in the upper region of a p-type silicon substrate 201, wherein the memory cell formation region 220 is surrounded by the trench isolations 202. A tunnel gate insulation film 205 is formed on the memory cell formation region 220. A first polycrystalline silicon film 206 is formed on the tunnel gate insulation film 205. A first silicon oxide film 221 is formed on the first polycrystalline silicon film 206. A first silicon nitride film 222 is formed on the first silicon oxide film 221. An antireflective film 223 is formed on the first silicon nitride film 222 to form multilayer laminations. A resist pattern 224 is formed on the antireflective film 223. An anisotropic etching process is carried out by use of the resist pattern 224 as a mask to pattern the multilayer laminations thereby forming a gate structure 225, which comprises the tunnel gate insulation film 205, the first polycrystalline silicon film 206, the first silicon oxide film 221, the first silicon nitride film 222 and the antireflective film 223. The used resist pattern 224 is removed.
With reference to FIG. 2B, a first ion-implantation process is carried out by use of the gate structure 225 as a mask for introducing an n-type impurity into selected upper regions of the memory cell formation region 220 except under the gate structure 225 thereby to selectively form nxe2x88x92-type lightly doped diffusion regions 204 in the selected upper regions of the memory cell formation region 220 except under the gate structure 225, wherein the nxe2x88x92-type lightly doped diffusion regions 204 are defined by the shallow trench isolation regions 202 and are self-aligned to the gate structure 225. An oxide film is entirely formed which extends over the shallow trench isolation regions 202, the nxe2x88x92-type lightly doped diffusion regions 204 and side walls and a top surface of the gate structure 225. An anisotropic etching process is then carried out to the oxide film so as to selectively leave the oxide film on the side walls of the gate structure 225, whereby side wall oxide films 209 are formed on the side walls of the gate structure 225. A second ion-implantation process is carried out by use of the gate structure 225 and the side wall oxide films 209 as a mask for introducing an n-type impurity into selected upper regions of the memory cell formation region 220 except under the gate structure 225 and the side wall oxide films 209 thereby to selectively form n+-type source and drain regions 203S and 203D in the selected upper regions of the memory cell formation region 220 except under the gate structure 225 and the side wall oxide films 209, wherein the n+-type source and drain regions 203S and 203D are defined by the shallow trench isolation regions 202 and are self-aligned to the side wall oxide films 209. As a result, the n -type lightly doped diffusion regions 204 remain under the side wall oxide films 209. The boundaries between the n+-type source and drain regions 203S and 203D and the nxe2x88x92-type lightly doped diffusion regions 204 are aligned to the outside edges of the side wall oxide films 209.
With reference to FIG. 2C, a first inter-layer insulator 210 is entirely formed over the shallow trench isolation regions 202, the n+-type source and drain regions 203S and 203D, the side wall oxide films 209 and the gate structure 225, whereby the side wall oxide films 209 and the gate structure 225 are completely buried within the first inter-layer insulator 210. The first inter-layer insulator 210 comprise a boro-phospho-silicate glass film. A planarization process is carried out to the first inter-layer insulator 210 and the gate structure 225 by a chemical mechanical polishing process, whereby upper regions of the first inter-layer insulator 210 and the gate structure 225 with the side wall oxide films 209 are removed, wherein the silicon nitride film 222 serves as a polishing stopper. The chemical mechanical polishing process is stopped soon after the top surface of the silicon nitride film 222 is shown. Namely, a planarized surface is formed, wherein a planarized top surface of the first inter-layer insulator 210 is leveled to the planarized top surface of the silicon nitride film 222 of the gate structure 225 and also leveled to the planarized top surface of the side wall oxide films 209. The silicon nitride film 222 is much slower in etching rate than the first inter-layer insulator 210, whereby the silicon nitride film 222 is sufficient in serving as the polishing stopper in the chemical mechanical polishing process, thereby preventing the first polycrystalline silicon film 206 from being polished.
With reference to FIG. 2D, the silicon nitride film 222 is removed. Further, the first inter-layer insulator 210 and the side wall oxide films 209 are selectively etched to the same level as the top surface of the first polycrystalline silicon film 206 of the gate structure 225. At the same time, the silicon oxide film 221 is also removed. As a result, an almost planarized surface is formed, wherein the a planarized top surface of the first inter-layer insulator 210 is leveled to the planarized top surface of the first polycrystalline silicon film 206.
With reference to FIG. 2E, a second polycrystalline silicon film 207 is entirely formed over the planarized top surfaces of the first inter-layer insulator 210, the side wall oxide films 209 and the first polycrystalline silicon film 206. The second polycrystalline silicon film 207 is then patterned to form a second polycrystalline silicon pattern 207. The second polycrystalline silicon pattern 207 has a width sufficiently covering the first polycrystalline silicon film 206. The second polycrystalline silicon pattern 207 extends along the column direction perpendicular to the width direction. An ONO inter-gate insulator 208 is entirely formed on the second polycrystalline silicon pattern 207 and the first inter-layer insulator 210. The ONO inter-gate insulator 208 comprises laminations of an oxide film, a nitride film and an oxide film. A third polycrystalline silicon film 211 is entirely formed on the ONO inter-gate insulator 208. Laminations of the third polycrystalline silicon film 211, the ONO inter-gate insulator 208, the second polycrystalline silicon pattern 207 and the first polycrystalline silicon film 206 are selectively etched or patterned to have the laminations extend in the row direction. The third polycrystalline silicon film 211 forms a control gate electrode as a word line. The first polycrystalline silicon film 206 and the second polycrystalline silicon pattern 207 form a floating gate electrode. As a result, the floating gate MOS field effect transistor is completed.
As described above, the conventional method utilizes the nitride film 222 which serves as a polishing stopper in the chemical mechanical polishing process, wherein the nitride film 222 is much larger in polishing selectivity than the first polycrystalline silicon film 206 and the first inter-layer insulator 210 of boro-phospho-silicate glass. Namely, the nitride film 222 is used as a dummy film. On the other hand, the resist film 224 is used for shaping the gate structure 225. The nitride film 222 has an etching selectivity of about 0.56 to the resist film 224. Namely, the nitride film 222 is lower in etching selectivity than the resist film 224. This means it difficult to form the nitride film 222 in highly accurate dimension or in highly accurate width. The resist film 224 overlying the antireflective layer 223 is used as a mask for selectively etching the antireflective layer 223, the nitride film 222, the silicon oxide film 221 and the first polycrystalline silicon film 206. The nitride film 222 is lower in etching selectivity than the resist film 224. Namely, the nitride film 222 is lower in etching rate than the resist film 224, for which reason opposite side edges of the resist film 224 are over-etched, whereby a horizontal size of the resist film 224 is reduced from the designed size, before the above gate structure 225 is completely defined by this etching process. The over-etched and size-reduced resist film 224 causes the nitride film 222 to be also over-etched in horizontal direction and to be reduced in horizontal size, whereby the nitride film 222 gradually varies in horizontal size, so that the horizontal size of the nitride film 222 is gradually reduced upwardly. namely, the side walls of the nitride film 222 are not vertical rather sloped. the cross sectional vertical shape of the nitride film 222 is trapezoid. The over-etched and size-reduced resist film 224 further causes the silicon oxide film 221 and the first polycrystalline silicon film 206 to be also over-etched in horizontal direction and to be reduced in horizontal size. The above horizontal size reductions of the nitride film 222, the silicon oxide film 221 and the first polycrystalline silicon film 206 means that the gate structure 225 is reduced in horizontal size. This means that the gate structure 225 is reduced in size in the gate length direction. The nxe2x88x92-type lightly doped diffusion regions 204 are self-aligned to the edges of the gate structure 225. The reduction in size in the gate length direction of the gate structure 225 causes variation in position of the inner edges of the nxe2x88x92-type lightly doped diffusion regions 204, whereby a channel length defined between the inner edges of the nxe2x88x92-type lightly doped diffusion regions 204 is reduced. This variation in channel length causes variations in characteristics and performances of the memory cells, for example, the necessary times of writing and erasing data, and ON-current for reading out data. This makes it difficult to realize advanced memory cells having 0.22 micrometers gate length.
In the above circumstances, it had been required to develop a novel method of forming a non-volatile semiconductor memory device free from the above problem.
Accordingly, it is an object of the present invention to provide a novel method of forming a non-volatile semiconductor memory device free from the above problems.
It is a further object of the present invention to provide a novel method of forming a non-volatile semiconductor memory device free from any substantive variation in channel length.
It is a still further object of the present invention to provide a novel method of forming a non-volatile semiconductor memory device being highly reliable in characteristics and performances.
It is yet a further object of the present invention to provide a novel method of forming a non-volatile semiconductor memory device free from any substantive variations in the necessary times of writing and erasing data, and in ON-current for reading out data.
It is another object of the present invention to provide a novel method of forming a gate structure of a floating gate MOS field effect transistor for a semiconductor memory device free from the above problems.
It is further another object of the present invention to provide a novel method of forming a gate structure of a floating gate MOS field effect transistor for a semiconductor memory device free from any substantive variation in channel length.
It is still further another object of the present invention to provide a novel method of forming a gate structure of a floating gate MOS field effect transistor for a semiconductor memory device being highly reliable in characteristics and performances.
It is yet further another object of the present invention to provide a novel method of forming a gate structure of a floating gate MOS field effect transistor for a semiconductor memory device free from any substantive variations in the necessary times of writing and erasing data, and in ON-current for reading out data.
The first present invention provides a method of patterning a conductive layer buried in an inter-layer insulator. The method comprises the steps of: forming a dummy layer over a conductive layer; selectively forming a resist pattern over the dummy layer; carrying out an anisotropic etching process for patterning the dummy layer and the conductive layer by use of the resist pattern as a mask; removing the resist pattern; forming an inter-layer insulator so that the dummy layer and the conductive layer are completely buried within the inter-layer insulator; carrying out a first planarization process for polishing the inter-layer insulator; and carrying out a second planarization process for selectively etching the inter-layer insulator, so that at least a top portion of the dummy layer is etched removing the dummy layer; carrying out a third planarization process for selectively etching the inter-layer insulator, so that a planarized surface of the inter-layer insulator is leveled to a planarized surface of the conductive layer, wherein the dummy layer has a higher etching selectivity to the inter-layer insulator than nitride.
The second present invention provides a method of forming a gate structure of a floating gate MOS field effect transistor. The method comprises the steps of: forming a conductive layer on a gate insulating film; forming a dummy layer over the conductive layer; selectively forming a resist pattern over the dummy layer; carrying out an anisotropic etching process for patterning the dummy layer and the conductive layer by use of the resist pattern as a mask, thereby to form a gate structure; removing the resist pattern; forming side wall insulation films on side walls of the gate structure; forming an inter-layer insulator so that the gate structure and the side wall insulation films are completely buried within the inter-layer insulator; carrying out a first planarization process for polishing the inter-layer insulator; and carrying out a second planarization process for selectively etching the inter-layer insulator and the side wall insulation films, so that at least a top portion of the dummy layer is etched; removing the dummy layer; carrying out a third planarization process for selectively etching the inter-layer insulator and the side wall insulation films, so that a planarized surface of the inter-layer insulator and the side wall insulation films is leveled to a planarized surface of the conductive layer, wherein the dummy layer has a higher etching selectivity to the inter-layer insulator than nitride.
The third present invention provides a dummy layer pattern provided over a conductive layer pattern buried in an inter-layer insulator for protecting the conductive layer pattern from being over-polished by a chemical mechanical polishing process, wherein the dummy layer pattern has a higher etching selectivity to the inter-layer insulator than nitride.
The above and other objects, features and advantages of the resent invention will be apparent from the following descriptions.